The present technique relates to integrated circuits. Specifically, the present technique relates to an integrated circuit that operates in synchronization with a timing signal.
It is known that, when the drive voltage of an integrated circuit including a circuit (e.g. flip-flop) that operates in synchronization with a timing signal such as a clock signal is lowered, variation in skew exponentially increases along with the lowering of the drive voltage. The skew is the difference between delay time until the timing signal reaches a certain circuit and delay time until the timing signal reaches a circuit different from this circuit.
The increase in the skew variation possibly causes the occurrence of a timing error in the circuit such as a flip-flop. The timing error refers to the occurrence of a malfunction in the circuit due to deviation of the timing when the timing signal reaches the circuit from the range supposed in the design.
To suppress this increase in the skew variation, a method for controlling an integrated circuit has been proposed. In this method, when the drive voltage is lowered, simultaneously the operating frequency of the integrated circuit is also lowered (refer to e.g. Japanese Patent Laid-open No. 2010-118746). By lowering the operating frequency at most to such an extent that a timing error does not occur, the power consumption is reduced with ensuring of the stable operation of the integrated circuit.